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2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Read and Write Access Modes
Figure 28: t FAW Timing (8-Bank Devices)
Tn
Tn+
Tm
Tm+
Tx
Tx+
Ty
Ty + 1
Ty + 2
Tz
Tz + 1
Tz + 2
CK#
CK
CA[9:0]
Bank Bank
A A
Bank Bank
B B
Bank Bank
C C
Bank Bank
D D
Bank Bank
E E
t RRD
t RRD
t RRD
CMD ACTIVATE
NOP
ACTIVATE
NOP
ACTIVATE
NOP
ACTIVATE
NOP
NOP
NOP
ACTIVATE
NOP
t FAW
Note:
1. Exclusively for 8-bank devices.
Read and Write Access Modes
After a bank is activated, a READ or WRITE command can be issued with CS# LOW, CA0
HIGH, and CA1 LOW at the rising edge of the clock. CA2 must also be defined at this
time to determine whether the access cycle is a READ operation (CA2 HIGH) or a
WRITE operation (CA2 LOW). A single READ or WRITE command initiates a burst
READ or burst WRITE operation on successive clock cycles.
A new burst access must not interrupt the previous 4-bit burst operation when BL = 4.
When BL = 8 or BL = 16, READs can be interrupted by READs and WRITEs can be inter-
rupted by WRITEs, provided that the interrupt occurs on a 4-bit boundary and that
t CCD is met.
Burst READ Command
The burst READ command is initiated with CS# LOW, CA0 HIGH, CA1 LOW, and CA2
HIGH at the rising edge of the clock. The command address bus inputs, CA5r–CA6r and
CA1f–CA9f, determine the starting column address for the burst. The read latency (RL)
is defined from the rising edge of the clock on which the READ command is issued to
the rising edge of the clock from which the t DQSCK delay is measured. The first valid
data is available RL × t CK + t DQSCK + t DQSQ after the rising edge of the clock when the
READ command is issued. The data strobe output is driven LOW t RPRE before the first
valid rising strobe edge. The first bit of the burst is synchronized with the first rising
edge of the data strobe. Each subsequent data-out appears on each DQ pin, edge-
aligned with the data strobe. The RL is programmed in the mode registers.
Pin input timings for the data strobe are measured relative to the crosspoint of DQS and
its complement, DQS#.
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
55
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
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